Jack Ou, Ph.D.

Assistant Professor, Eletrical and Computer Engineering, California State University
Ph,D., M.S., and B.S. Rutgers University (Piscataway Campus)
Research Interest: CMOS analog/RF integrated circuits

Research Overview
The mission of the Circuits and Systems Laboratory is to develop technologies that enable wireless communication of devices. The ultimate goal is to enable deployment of intelligent sensor nodes through wireless standards such as IEEE 802.11ah and IEEE 802.15.6.

At the undergraduate level, the research is focused on using existing technologies to solve problems that affect everyday living. At the graduate level, the research and development effort is focused on developing key integrated circuit building blocks/techniques that are crucial to deployment of low power wireless sensor nodes in the near future. In particular, we focus on:

  1. Techniques that enhance analog design productivity.
  2. Techniques that automate design of analog/radio frequency circuits
  3. Techniques that enable characterization of analog and RF circuits.

Selected publications:
1. Ou, J. and Ferreira, P., “A Transconductance/Drain Current Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier,” IEEE Transaction of Circuits and Systems II, October, 2014.
2. Ou, J., and Ferreira, P., “A Unified Explanation of Transconductance/Drain Current Based Noise Analysis,” Journal of Circuits, Systems and Computers, January, 2015.
3. Caggiano, M.F., Ou, J., Bulumulla, S., Lischner, D., “RF electrical measurements of fine pitch BGA packages,” IEEE Transactions on Components and Packaging Technologies, Part A: Packaging Technologies, Volume: 24, Issue: 2, June 2001, Pages: 233-240.
4. Ferreira, P. M., Ou, J., and C. Gaquiere, “Automated System-Level Design for Reliability: RF Front-End Application,” Computational Intelligence in Electronic Design, Springer.

Previous Projects:
  • Transconductance/Drain Current Based Sensitivity/Distortion/Noise Design Methodology
  • VerilogAMS Verification of a Low Density Parity Code (LDPC) Forward Error Correction Ciruit
  • Voltage Controlled Oscillator in 180 nm/65 nm CMOS
  • A WCDMA Downconverter circuit in 90nm/65 nm CMOS
  • A High Frequency Distributed Current Commutating Mixer
  • Inductor/Transformer/Transmission Line Modeling
  • Inductance Calculation of Complex Internnect