Course:Digital Circuits and Logic Design (ES 210)
Section: 001
Spring, 2014

homework/syllabus

Instructor:  Jack Ou, Ph.D.
Office Location: Salazar Hall 2010B
Telephone: (707) 664 3462
Email:jack.ou AT sonoma DOT edu
Office Hours: By appointment, M 1:00-2:00, TTH 10:15-10:45.
Class Days/Time: MW 2:00-3:15 (Lectures), Thursdays 1:00 -3:50 (Lab)
Classroom: Salazar Hall 2009A/Sal 2005
Prerequisites: ES 112
Co-requisites: ES 230

Course Description

Logic gates, combinatorial logic and analysis and design of combinatorial circuits, electronic circuits for various logic gates. Flip-flops, registers, and counters, sequential circuits and state machines. Various logic families and comparison of their electrical characteristics such as fan-out, rise and fall times, delay, etc. Concepts of machine, assembly and high level languages and relationship between them, basic principles of computer design. Laboratory work will include designing, building and testing of digital circuits, logic and sequential circuits.

Required Materials:
1.  M. Morris Mano and Michael D. Ciletti, “Digital Design”, 4th Edition, Prentice Hall, ISBN 0-13-198924-3
2. Laboratory Manual

 

Laboratory Supplies:

Laboratory Supplies (Required, supplies you should have gotton in ES221. You are responsible for getting these components. You are not required to buy from the same suppliers. You may split the cost with your lab partner.)

Discrete Components (Optional, Components on this list will be provided by the department. This list is provided here for students who wish to get their own components)

Datasheets, list of 7400 TTL gates

Tutorials: emacs, vi & verilog, youtube tutorial.

Date
Topic
Description
1/13
course intro, diagnostic test
1/15
first verilog program
introduce verilog
1/16
first verilog program
verilog experiment
1/20 mlk (no class)  
1/22
more on verilog
include file, random test vector
1/23 verilg modeling of a nand based nor flip_me, flip_me_tb, nor_with_nand, nor_with_nand_tb, bit_str_a_0, bit_str_a_1.
1/27
nand based nor on a breadboard
74ls00 chip
1/29
half adder
$monitor, $fmonitor, assign, bitwise logic opeartor, half adder
1/30
half adder
half_adder.v
2/3
wire vs. reg
wire vs. reg, blocking statement, non-blocking statements
2/5
full adder,hw1
a0,a1,a2,a3,b0,b1,b2,b3,c0,half_adder.v, half_adder_tb.v
2/12
subtractor/multiplier,hw2
delay, subtractor, multiplier.
2/17
decoder
decoder
2/19
encoder, hw3
encoder, encode83.v, encode83_tb.v, encode83_tb.out
2/24
mux
dataflow modeling vs. behavioral modeling
2/7
modeling styles
lab files: 1, 2, 3, 4, 5, 6, 7
3/3
modeling styles
more examples
3/5
midterm, review sheet, hw3 solution.
3/10
latches
sr latch, d latch
3/12
flip-flops
d flip-flop, jk flip-flop, t flip-flop
3/24
sequential circuit (1)
logic synthesis demo
3/26
sequential circuit (2), hw4
3/27
sequential circuit lab
fig5p16.v, fig5p16_tb.v
3/31
no class
4/2
shift register
worksheet
4/3
shift register lab
0,1,2,3,msb, lsb, beh, beh_tb
4/7
counter,hw5
worksheet
4/9
review
hw4_sol, hw5_sol
4/10
counter lab
4/14
test #2
class 1,2,3,4, 5
courtesy of ryan hirth