Course:Digital Circuits and Logic Design (ES 210)
Section: 001
Spring, 2013

 

Instructor:  Jack Ou, Ph.D.
Office Location: Salazar Hall 2010B
Telephone: (707) 664 3462
Email:jack.ou AT sonoma DOT edu
Office Hours: By appointment during MW10:15-10:45 and TH 12:30-1
Class Days/Time: MW 1:00-2:15. Lab: T 1:00-3:45 (SAL 2003)
Classroom: Salazar Hall 2009A
Prerequisites: ES 112
Co-requisites: ES 230

Course Description

Logic gates, combinatorial logic and analysis and design of combinatorial circuits, electronic circuits for various logic gates. Flip-flops, registers, and counters, sequential circuits and state machines. Various logic families and comparison of their electrical characteristics such as fan-out, rise and fall times, delay, etc. Concepts of machine, assembly and high level languages and relationship between them, basic principles of computer design. Laboratory work will include designing, building and testing of digital circuits, logic and sequential circuits.

Required Materials:
1.  M. Morris Mano and Michael D. Ciletti, “Digital Design”, 4th Edition, Prentice Hall, ISBN 0-13-198924-3
2.  Basys 2 Spartan-3E FPGA Board.  (49.00)

3. Digital Design Using Digilent FPGA Boards (44.95, Verilog edition)

4. ES210 Lab manual

5. Hardware components , list of 7400 TTL gates.

 

syllabus, project ideas

date
topic
description
1/14
introduction
1/15
no lab!
1/16
555 timer, tutorial
555 timer ic, ring oscillator, astable multivibrator, monostable circuit
1/21
mlk day
1/22
555 timer ic
1/23
adc/dac, adc demo, dac tutorial
adc, dac
1/28
intro to basys 2
basys2
1/29
basys 2, license site, basys2.ucf
first basys2 lab
1/30
implement a full adder using fpga, demo, gates2
verilog syntax, gate delay, test bench,implement a full adder on fpga.
2/4
led display
karnaugh map, hex to seven-segment display,
2/5
full adder,demo
verilog/74xx implementation of a full adder
2/6
led display (2)
display one led at a time, always, wire versus reg, mux
2/11
binary addition and subtraction
carry_lookahead demo, ripple adder, binary adder with fast carry, implement a subtractor using an adder
2/12
4-bit binary adder with fast carry
verilog modeling and 7483 four bit adder with look-ahead carry
2/13
4-bit adder and subtractor
2/18
n/a
2/19
implment binary add/subtractor
2/20
test #1
2/25
pcb fabrication
pcb layout
2/26
intro to eagle
verilog files, revise schematic,practice pcb layout,autorouter.ctl, design_rule.dru
2/27
verilog model of binary adder, binary multiplication, magnitude comparator
2-bit binary multiplier, adder-based multiplier circuits, magnitude comparator
3/4
decoder, pcb layout
test bench generation, decoder
3/5
pcb fabrication
3/6
encoder
3/11
latches
sr latch, d-latch
3/26
d-latch experiment
b_ran_bits.m, t_vector.v
3/27
flip-flops
d flip-flop, jk flip-flop, t flip-flop, phase-frequency detector
4/2
d-latch with random number generator
mixed signal scope, random number generator
4/3
analysis of clocked sequential circuit
state diagram, synthesis using d flip-flop
4/8
verilog modeling of fsm
4/9
design a mealy type fsm (lab)
fig5p16,fig5p16_tb
4/10
registers, shift registers
serial adder, shift register, universal shift register
4/15
verilog modeling of shift register
final project
4/16
shift registers lab
sr_beh, sr_str, sr_beh_tb, sr_str_tb
4/17
counters
4/18
overview of digital ic design from 4:30 to 5:30 pm.
4/22
ring counter, verilog modeling of counter
proposal for final project due
4/23
counters lab
meet to discuss project. begin to work on the final project!
4/24
memory
4/29
review, wrap-up
4/30
sram lab
5/1
test #2
5/8
final project due
2-3:50 pm