Course:Fundamentals of Digital Logic Design (ES 112)
Section: 001
Spring, 2011

Syllabus

Instructor:  Jack Ou, Ph.D.
Office Location: Salazar Hall 2010B
Email:jack.ou AT sonoma DOT edu
Class location: Salazar Hall 2009A
Office Hours: By appointment during MW10:15-10:45 and TH 12:30-1

Course Description:

Review of set theory and binary system, digital logic, Venn diagram, logic gates, minimization techniques, combinatorial logic and design of simple combinatorial logic circuits such as 1-bit adder; concept of coders, decoders and integrated circuits.

Required Textbooks: 

M. Morris Mano and Michael D. Ciletti, “Digital Design”, 4th Edition, Prentice Hall, ISBN 0-13-198924-3.

Date
Topic
Reference
Homework
Due Date
Solution
1/19
introduction
n/a
n/a
n/a
n/a
1/26
numbers, notes
1.2-1.4
hw1
2/2
hw1s
2/2
addition/subtraction
1.5-1.6
hw2
2/9
hw2s
2/9
demos/discussion
n/a
n/a
n/a
n/a
2/16
binary logic/boolean algebra
1.9, 2.1-2.4
hw3
2/23
hw3s
2/23
sum of products
2.5-2.6
hw4
3/1
hw4s
3/1
digital logic gates
2.7-2.8
practice
n/a
practice_sol
3/8
quiz 1
1-2
n/a
n/a
n/a
3/15
review
3/22
karnaugh map
3.1-3.4
hw5
n/a
3/29
spring break
n/a
n/a
n/a
4/5
quiz 2, project discussion
n/a
n/a
n/a
4/12
error detection and correction
3.6-3.9
n/a
n/a
4/19
quiz 3,
binary addition
4.5
4/26
subtraction/multiplication
4.7-4.11
5/3
quiz 4, wrap-up
5/10
final,2:00 p.m.-3:50 p.m.